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general description the max4455 is an eight-channel arbitrary graphics on-screen display (osd) video generator that inserts arbitrary gray-scale bit-mapped graphics into eight asynchronous composite video sources. ideal for secu- rity camera surveillance systems, the max4455 sup- ports the insertion of graphics and text on up to eight video output channels in 15 levels of brightness. it easi- ly displays information such as company logo, camera location, time, and date with arbitrary fonts and sizes. arbitrary graphics capability enables the display of unique languages and fonts, allowing manufacturers to tailor their system for any geographic market. the max4455 is designed to work with maxim? video crosspoint switches, such as the max4356 and max4358, which include circuitry that simplifies the insertion of the osd information. the max4455 can also be used with discrete fast mux switches. the max4455 operates from a 3v to 3.6v digital sup- ply, and a 2.7v to 5.5v analog supply. independent interface supplies enable the max4455 to communi- cate with microprocessors and osd crosspoint switch logic with logic levels ranging from 2.7v to 5.5v. the max4455 uses an external 16mb sdram for graphical image storage for all eight video channels. the max4455 manages all memory interface functions, allowing a simple host ? interface. the max4455? multiple-channel memory sharing and multiple-location write function allow fast memory updates of shared graphics information necessary for rapidly changing osd information, such as a time stamp. the max4455 is available in a thin 100-pin tqfp pack- age (200mm 2 area), and is fully specified over the extended temperature range (-40 c to +85 c). the max4455evsys is available to evaluate the max4455 along with the max4358 (32 16 video crosspoint switch with osd). applications security systems video routing industrial applications features generates arbitrary graphics images 15-level gray scale 8 channels of bit-mapped osd loss-of-signal detector for all channels graphics updatable within the vertical interval update time stamp on all eight channels simultaneously 3v and 5v single-supply operation works with max4356/max4358 video crosspoint devices and fast mux switches small 100-pin tqfp package (200mm 2 ) max4455 arbitrary graphics on-screen display video generator ________________________________________________________________ maxim integrated products 1 vidin0 osdfill0 4-bit d/a osdfill1 osdfill7 osdkey0 osdkey1 osdkey7 osdfill2 osdkey2 video timing extraction digital line buffers 4-bit d/a 4-bit d/a 4 bit d/a memory interface 16 osd control and timing xtal1/sync 11 memory address bus memory data bus ck ba vidin1 vidin2 vidin7 cpu interface dac current ref rset 8 ad7?d0 addr/data rdy/bsy rd wr cs v h1 v k1 we cas dq ras xtal2 agnd av dd dgnd dv dd max4455 video timing extraction video timing extraction video timing extraction digital line buffers digital line buffers digital line buffers ordering information 19-2463; rev 2; 3/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max4455ecq -40 c to +85 c 100 tqfp pin configuration appears at end of data sheet. functional diagram
max4455 arbitrary graphics on-screen display video generator 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to dv dd .............................................................-6v to +6v av dd to agnd .........................................................-0.3v to +6v av dd to dgnd .........................................................-0.3v to +6v dv dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v v h1 , v k1 to dgnd....................................................-0.3v to +6v v h1 , v k1 to agnd ....................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v analog inputs (vidin_) to agnd .............-0.3v to (av dd + 0.3v) analog outputs (osdfill_) to agnd .....-0.3v to (av dd + 0.3v) rset to agnd .........................................-0.3v to (av dd + 0.3v) memory interface to dgnd .....................-0.3v to (dv dd + 0.3v) host interface to dgnd ..............................-0.3v to (v h1 + 0.3v) osdkey_ to dgnd.....................................-0.3v to (v k1 + 0.3v) continuous power dissipation (t a = +70 c) 100-pin tqfp (derate 37.0mw/ c above +70 c).......2963mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (dv dd = 3.0v to 3.6v, av dd = 2.7v to 5.5v, v k1 = v h1 = 2.7v to 5.5v, agnd = dgnd = 0, r rset = 11.75k ? 1%, r osdfill_ = 75 ? , f xtal1/sync = 40.5mhz, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units analog supply voltage av dd 2.7 5.5 v digital supply voltage dv dd 3.0 3.6 v host supply voltage v h1 2.7 5.5 v osdkey logic supply voltage v k1 2.7 5.5 v analog supply current ai dd all osdfill_ outputs at 100 ire 190 ma digital supply current di dd f xtal1/sync = 40.5mhz 30 ma host interface static supply current i vh1 host interface logic levels driven to gnd or v h1 10 a analog power-supply rejection ratio psrr at dc 35 db vidin_ input resistance 100 k ? osdfill slew rate sr output v p-p = 0.7v 140 v/s av dd = 2.7v -8.2 +8.2 white output voltage accuracy fsr pixel data = 1111 av dd = 5.5v -7.5 +7.5 ire black output voltage pixel data = 0001 1.5 ire osdfill dac linearity (guaranteed monotonic) 5 %fsr channel-to-channel crosstalk at 6mhz v out = 0.7v p-p 60 db key-to-fill timing delay 1 ns rset pin voltage 0.80 v osdkey_ logic output low v ol v k1 = 5v, i sink = 4ma 0.45 v osdkey_ logic output high v oh v k1 = 5v, i source = 4ma 2.4 v osdkey_ logic supply current i vk1 osdkey_ logic levels driven to gnd or v k1 10 a
max4455 arbitrary graphics on-screen display video generator _______________________________________________________________________________________ 3 ? host interface?c characteristics (dv dd = 3.0v to 3.6v, av dd = 2.7v to 5.5v, v k1 = v h1 = 2.7v to 5.5v, agnd = dgnd = 0, r rset = 11.75k ? 1%, r osdfill_ = 75 ? , f xtal1/sync = 40.5mhz, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units logic input voltage low v il ( 0.2 v h 1 ) - 0.1 v logic input voltage high v ih ( 0.2 v h 1 ) + 1.2 v logic input current i il / i ih sinking or sourcing 10 a logic output low v ol v h1 = 5v, i sink = 4ma 0.45 v logic output high v oh v h1 = 5v, i source = 4ma 2.4 v p host interface ac characteristics (dv dd = 3.0v to 3.6v, av dd = 2.7v to 5.5v, v k1 = v h1 = 2.7v to 5.5v, agnd = dgnd = 0, r rset = 11.75k ? 1%, r osdfill_ = 75 ? , f xtal1/sync = 40.5mhz, c host = 50pf, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) (figure 1) parameter symbol conditions min typ max units cs, add/ data , ad7 ad0 setup time before wr deassertion t 1 30 ns cs hold after wr deassertion t 2 30 ns read data access time t 4 (note 3) 50 ns read data out to high-z time t 5 15 25 ns clock timing characteristics (dv dd = 3.0 to 3.6v, av dd = 2.7v to 5.5v, v k1 = v h1 = 2.7v to 5.5v, agnd = dgnd = 0, r rset = 11.75k ? 1%, r osdfill_ = 75 ? , f xtal1/sync = 40.5mhz, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 4) (figure 2) parameter symbol conditions min typ max units master clock frequency f clkin crystal oscillator or externally driven for specified performance 40.5 40.6 mhz master clock input low time t clcx t clkin = 1 / f clkin (note 6) 10 ns master clock input high time t chcx t clkin = 1 / f clkin (note 6) 10 ns memory interface dc characteristics (dv dd = 3.0v to 3.6v, av dd = 2.7v to 5.5v, v k1 = v h1 = 2.7v to 5.5v, agnd = dgnd = 0, r rset = 11.75k ? 1%, r osdfill_ = 75 ? , f xtal1/sync = 40.5mhz, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units logic input voltage low v il ( 0.2 d v d d ) - 0.1 v logic input voltage high v ih ( 0.2 d v d d ) + 1.3 v logic input current i il / i ih sinking or sourcing 10 a logic output low v ol dv dd = 3.3v, i sink = 4ma 0.45 v logic output high v oh dv dd = 3.3v, i source = 0.5ma 2.4 v
max4455 arbitrary graphics on-screen display video generator 4 _______________________________________________________________________________________ memory interface timing characteristics (dv dd = 3.0v to 3.6v, av dd = 2.7v to 5.5v, v k1 = v h1 = 2.7v to 5.5v, agnd = dgnd = 0, r rset = 11.75k ? 1%, r osdfill_ = 75 ? , f xtal1/sync = 40.5mhz, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units digital output maximum rise time t clch 15pf load (note 5) 3 ns digital output maximum fall time t chcl 15pf load (note 5) 3 ns maximum digital out to digital out skew t skew 15pf load, except d0 d15 2.5 ns note 1: f xtal1/sync is production tested at 1mhz. application operating frequency is f xtal1/sync = 40.5mhz. note 2: pertains to host interface pins: addr/ data , cs, wr , rd , ad7 ad0, rdy/ bsy . v h1 is connected to p host power supply rail (2.7v to 5.5v). note 3: read operation is combinational. access time is from the latter of either rd or cs. note 4: pertains to xtal1/syncin and xtal2 pins (external clock is supplied to xtal1/syncin pin). all input signals are specified with t r = t f = 5ns (10% to 90% of dv dd ), and timed from a voltage level of 1.6v. note 5: specified using 10% and 90% points. t chcx v ih v ih t clcx t chcl t clch xtal1/sync memory logic i/o v il v il ad7 ad0 wr add/data ad7 ad0 rd add/data host address or data write operation host data read operation t 1 t 2 t 3 t 4 t 5 cs cs addr/data in read data out figure 2. clock and memory timing diagram figure 1. ? host interface timing timing diagrams
max4455 arbitrary graphics on-screen display video generator _______________________________________________________________________________________ 5 full-scale output vs. r rset max4455 toc01 r rset (k ? ) full-scale output (ire) 14 13 11 12 6 7 8 9 10 5 25 50 75 100 125 150 175 200 225 0 415 dac output vs. dac code max4455 toc02 dac code dac output (ire) 14 13 11 12 4 5 6 7 8 9 10 2 3 10 20 30 40 50 60 70 80 90 100 110 0 115 r rset = 11.75k ? dac output vs. dac code vs. r rset max4455 toc03 dac code dac output (ire) 14 13 11 12 4 5 6 7 8 9 10 2 3 25 50 75 100 125 150 175 200 225 0 115 r rset = 5.716k ? r rset = 7.636k ? r rset = 17.516k ? r rset = 14.598k ? r rset = 11.75k ? video line output with osd max4455 toc04 10 s/div a b c d 0 0 0 0 a: v camera (ntsc composite), 500mv/div b: v camera + osdfill , 500mv/div c: v osdfill , 500mv/div d: v osdkey , 5v/div note: measurement made with max4455evsys. video line output with osd (expanded time scale) max4455 toc05 1 s/div a b c d 0 0 0 0 a: v camera (ntsc composite), 500mv/div b: v camera + osdfill , 500mv/div c: v osdfill , 500mv/div d: v osdkey , 5v/div note: measurement made with max4455evsys. typical operating characteristics (av dd = 5v, dv dd = 3.3v, r rset = 11.75k ? , t a = +25 c, unless otherwise noted.)
max4455 arbitrary graphics on-screen display video generator 6 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd = 5v, dv dd = 3.3v, r rset = 11.75k ? , t a = +25 c, unless otherwise noted.) figure 3. on-screen display capability of the max4455
max4455 arbitrary graphics on-screen display video generator _______________________________________________________________________________________ 7 pin description pin name function 2, 1, 100, 99, 98, 97, 96, 95 vidin0 vidin7 analog video inputs. the max4455 extracts video timing information from each vidin_ input. ac-couple the input signal with a 0.1f capacitor. 3v h1 host interface supply voltage input. v h1 supplies the level shifters for logic outputs to the host p interface. connect v h1 to the p logic supply. 4, 25, 33, 42, 50, 58, 66, 72, 75 dgnd digital ground 5 cs host chip select digital input. drive cs logic high to enable the host data interface. 6 wr host write strobe digital input 7 rd host read strobe digital input 8 addr/ data host address or data select digital input 9 16 ad7 ad0 host address/data bus digital i/o 17 rdy/ bsy host ready/busy handshake digital output 18 23, 26, 27, 37, 36, 35, 34, 31, 30, 29, 28 d0 d15 memory data digital i/o 24, 32, 41, 49, 57, 71 dv dd positive digital power supply. bypass each dv dd pin with a 0.1f capacitor to dgnd. 38 dqm memory dqm digital output. dqm controls the memory output buffer in read mode, and masks input data in write mode. 39 clk memory clock digital output 48 we memory write enable digital output 51 cas memory column address strobe digital output 52 ras memory row address strobe digital output 53 ba memory bank address digital output 55, 56, 59, 60, 47, 46, 45, 44, 43, 40, 54 a0 a10 memory address digital outputs 61 64, 67 70 osdkey0 osdkey7 osdkey digital outputs. osdkey_ logic low controls the fast mux switches (available in the maxim crosspoint switches, max4356/max4358) to insert osdfill_ signal. 65 v k1 osdkey interface power-supply input. v k1 supplies the level shifters for osdkey_ logic outputs to the fast mux switches (available in the maxim crosspoint switches, max4356/max4358). connect v k1 to the digital supply of the fast mux switches (v dd of the max4356/max4358). 73 xtal1/sync crystal oscillator/external clock input. connect a crystal oscillator module to xtal1/sync, or connect a fundamental mode crystal oscillator between xtal1/sync and xtal2. 74 xtal2 crystal oscillator output. leave xtal2 unconnected when using a crystal oscillator module, or connect a fundamental mode crystal oscillator between xtal1/sync and xtal2. 76, 78, 80, 82, 84, 86, 88, 90, 92 av dd positive analog power supply. bypass each av dd pin with a 0.1f capacitor to agnd. 77, 79, 81, 83, 85, 87, 89, 91 osdfill7 osdfill0 osdfill analog outputs. osdfill_ are video dac current outputs and require a termination resistor (nominally 75 ? ) to agnd.
max4455 arbitrary graphics on-screen display video generator 8 _______________________________________________________________________________________ detailed description the max4455 provides 4-bit gray-scale graphics video to eight simultaneous independent composite video inputs. the bit-mapped approach allows an arbitrary message to be inserted into the camera video when used in conjunction with the max4356/max4358 video crosspoint switch or discrete fast mux switch. the inserted graphics can include camera location, date, time, company logo, or warning prompts. the graphics palette for each of the eight video channels in the max4455 is logically organized into 1024 pixels by 512 lines. this memory arrangement facilitates easy row/column pixel addressing by the host processor. the actual displayed area is 712 484 ntsc (712 512 pal) pixels. the remaining 312 logical pixels per line are blanked. the remaining 28 ntsc (0 pal) horizontal lines are also blanked as shown in figure 4. the max4455 controls a 16mb sdram (such as mt48lc1m16a) that stores video graphics insertion data. the max4455 performs all sdram support functions, including refresh, ras/cas timing, video addressing, and cpu access cycles for host processor read/write support. since the sdram is organized as a 16-bit wide 1 mil- lion deep array, each sdram memory location holds 4 pixels (based on the fact that a pixel is 4 bits and mem- ory is 16 bits wide). the host processor thus accesses pixels four at a time. the host processor interface is 8 bits wide so the 16 bit wide sdram data is written into (or read from) the pixel data register as two separate 8-bit bytes. the max4455 establishes a video raster time base by sensing the video signal on either the output of the maxim crosspoint switch, or the output buffer of the fast mux switch. the max4455 uses this raster timing to produce an osd image signal that can be inserted into the camera video by controlling the osdkey input to the maxim crosspoint switch or fast mux switch. the osd image is inserted wherever the osd video level pixel code has a nonzero value, and the crosspoint switch or discrete fast mux is made to pass the original video wherever the osd video level pixel code is zero. when the osd video level is nonzero, it represents a gray-level code such that level 1 is near black and code 15 (the maximum possible with a 4-bits-per-pixel code) is maximally white (table 1). the host computer fills the external osd frame memory with a bit-mapped image such that each pixel has a value between zero and 15, controlling both insertion locations and the brightness levels within an inserted video image. there are eight channels in the max4455 that share memory resources but are logically completely independent. writing/reading image data to/from any channel s mem- ory does not disrupt other channels. the max4455 features a memory-sharing function where the even channels or the odd channels can be updated simultaneously by writing to a designated source channel. the memory-sharing function mini- mizes the number of memory writes by the host proces- sor. this is useful for updating information that changes rapidly (i.e., time stamp). video inputs the max4455 s eight vidin_ inputs include circuitry to extract video timing from each asynchronous video channel for proper display of the osd specific to that channel. each vidin_ time-base circuitry includes a horizontal sync detector, vertical sync detector, vertical interval detector, horizontal line counter, and even/odd field counter. the vidin_ inputs sense a standard 1v p-p video signal at the output of the crosspoint switch, or fast mux buffer in order to make video timing insensitive to delays through the switch/mux. ac-couple the input with a 0.1f capacitor. osdfill_ video outputs the max4455 has eight independent current output video dacs that provide 7 ire to 100 ire video levels (r rset = 11.75k ? ) when terminated with 75 ? to agnd. connect osdfill_ to either the osdfill_ input of the maxim crosspoint switch (max4356/ max4358) or to one of the inputs of the fast mux switch. osdkey control outputs each osd channel has an osdkey_ logic output that drives low when osdfill_ output video is to be multi- plexed into the active video. the osdkey_ output interfaces directly to the osdkey_ inputs of the max4356/max4358 or control inputs of the fast mux switch to allow pixel-by-pixel osd insertion. the v k1 supply sets the osdkey_ logic output voltage levels. pin description (continued) pin name function 93 rset osdfill reference voltage. connect a resistor (typically 11.75k ? ) from rset to agnd to set the full-scale output current of all eight osdfill_ outputs. 94 agnd analog ground
max4455 arbitrary graphics on-screen display video generator _______________________________________________________________________________________ 9 connect v k1 to the max4356/max4358 v dd logic sup- ply, or a 5v logic supply for ttl output compatibility. osdfill_ reference voltage (rset) set the video dac s full-scale output current for all eight channels by connecting a resistor between rset and ground. the nominal 11.75k ? r rset provides a 100 ire video output level when osdfill_ outputs are terminated with 75 ? resistors to ground. r rset can typ- ically range between 5k ? and 15k ? . the full-scale osd dac output current = (106.5) / r rset . the full-scale osd dac output voltage is the osd dac output current r osdfill , where rosdfill_ is the termi- nation resistor to agnd at osdfill_. crystal oscillator the max4455 requires a 40.5mhz clock. connect a 3.3v crystal oscillator module to xtal1/sync and leave xtal2 unconnected, or connect a lower cost 40.5mhz fundamental mode crystal between xtal1/sync and xtal2. the max4455 is designed to operate with a 50% clock duty cycle, but typically operates with up to 40% to 60% duty cycles. the oscillator circuitry typically requires 10ms to settle after the dv dd supply is powered up. microprocessor interface the max4455 p interface includes a byte-wide address/data bus (ad7 ad0) for parallel programming of the max4455, write strobe input ( wr ), read strobe input ( rd ), active-high chip-select input (cs), address or data-select input (addr/ data ), and a ready/busy hand-shaking output (rdy/ bsy ) (figures 5 and 6). the max4455 allows for interfacing to a p powered from a different supply than the max4455 by connecting v h1 to the p supply. for example, the max4455 can be operated with a single 3.3v supply, while the p inter- face can be operated with 3.3v or 5v logic levels by connecting v h1 to the p power supply. host access protocol sequence 1) host sets add/ data = 1. 2) host outputs register address on ad7 ad0. 3) host pulses wr low, then high to write register address. 4) host checks rdy/ bsy = 1 (host waits if rdy/ bsy = 0). for register data writes: 1) host sets add/ data = 0. 2) host drives register data on ad7 ad0. 3) host pulses wr low, then high. for register data reads: 1) host removes drive from ad7 ad0 in anticipation of register read operation and sets add/ data = 0. 2) host then pulses rd low and reads register data. 3) the max4455 three states when rd is deasserted (high). sdram memory interface the max4455 interfaces directly to a 16mb sdram with 16-bit-wide data bus. the max4455 performs all sdram support functions, including refresh, ras/cas timing, data addressing, and cpu access cycles for host processor read/write support. max4455 register description osd register organization the host processor controls each of the max4455 s eight video channels through eight groups (blocks) of 8- bit command, status, data, and address registers, plus one multichannel register block. the register set descrip- tion for a single channel is described in table 2. the eight identical sets of 16 registers (14, plus 2 reserved) are selected by 4 lsb bits in the host interface address field as described in tables 3 and 4. the lower address bits select which register is accessed within any given channel. even channels can share buffer data for display pixel data gray scale description 0000 0 transparent no osd insertion. background video appears normally. 0001 1 7 ire (black) 0010 2 13 ire 0011 3 20 ire 0100 4 27 ire 0101 5 33 ire 0110 6 40 ire 0111 7 47 ire 1000 8 53 ire 1001 9 60 ire 1010 10 67 ire 1011 11 73 ire 1100 12 80 ire 1101 13 87 ire 1110 14 93 ire 1111 15 100 ire (white) table 1. pixel data mapping (4 bits per pixel)
max4455 arbitrary graphics on-screen display video generator 10 ______________________________________________________________________________________ among even channels. odd channels can also share buffer data for display among odd channels (see the memory sharing section). detailed description of the channel-n block registers qph, qpl (quad pixel register) read/write pixel data 16-bits at a time to the quad pixel registers due to the sdram memory organization. the 4 msbs (nybble) of qph represent the left-most pixel and the 4 lsbs of qpl represent the right-most pixel (4 bits per pixel). to transfer the qph/qpl value into display memory, set the qphoriz/qpline registers and then write 0000 0010 to the command register (see command register section). qphoriz this 8-bit value is the address of the quad pixel within the line specified by qpline hi and qpline lo. a zero in qphoriz addresses the leftmost displayed quad pixel in the specified line, and increasing qphoriz addresses indexes towards the right-hand side of the video screen. valid values range from zero to 177. write a 1 in the hinc bit of the channel status register to enable autoincrement of qphoriz. qphoriz autoincrement saturates at 177. qplineh, qplinel the qpline_ 9-bit address specifies the horizontal line of the quad pixel to be accessed (host read or write). the 9th bit resides in the lsb position (bit 0) of the qplineh register. the lower 8 bits of the 9-bit address are specified by qplinel. table 5 shows valid dis- played line numbers. note that for ntsc, lines 1 through 20 are never valid, as this is the vertical blank interval. write a 1 in the vinc bit of the channel status register to enable autoincrement of qpline_. qpline_ autoincrement saturates at 511. vertical 1 (20 ntsc lines, 25 pal lines) vertical 2 (21 ntsc lines, 26 pal lines) hblank hblank 525h / 625h per frame 712t ntsc, 702t pal approx 144t ntsc, 162t pal hblank pixel count is dependent upon incoming video hline period fld2: 263h/ 313h (pal) fld1: 262h/ 312h (pal) field 1 active video (242h ntsc, 287h pal) field 2 active video (242h ntsc, 287 pal) t frame = 33.367ms t = 1 / (13.5mhz) = 74.074ns = 1 pixel time 1st displayed pixel position is controlled by hoffset register figure 4. osd raster dimensions max4455 p digital supply 2.7v to 5.5v data bus wr rd add/data p host interface p ad7 ad0 rdy/bsy cs gpio 8 v cc v h1 dv dd max4455 digital supply 3v to 3.6v figure 5. ? host interface
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 11 status the channel status register contains a group of individ- ual control bits and a loss-of-sync (los) flag bit. blank (when set to 1) forces suppression of the osd insertion graphics, independent of the memory contents. async (when set to 1) enables the shrxxxx registers to be updated by the host immediately; otherwise, they are updated at the next complete video field. hinc (when set to 1) enables autoincrement of the qphoriz regis- ter after each host read/write to osd memory. vinc (when set to 1) enables autoincrement of qplineh/l after each host read/write to osd memory. the los flag is useful in detecting the presence (or absence) of com- posite video at the channel vidin_. los is a 1 if the channel s valid composite sync is lost for more than one horizontal line period. it resets back to zero once a valid sync pulse is detected. ad7 ad0 wr add/data host address and data write operation host address and data read operation address cs data in high-z rd ad7 ad0 wr add/data address cs data out high-z rd figure 6. host data write and read sequences the channel status register is described below: bit7 bit0 0 0 0 vinc hinc async blank los
max4455 arbitrary graphics on-screen display video generator 12 ______________________________________________________________________________________ address name description 0nnn0000 qph quad pixel high data read/write. most significant nybble = leftmost pixel. 0nnn0001 qpl quad pixel low data read/write. least significant nybble = rightmost pixel. 0nnn0010 qphoriz quad pixel within h line address 0nnn0011 qplineh quad pixel line address high 0nnn0100 qplinel quad pixel line address low 0nnn0101 status loss of sync for channel n, control bits 0nnn0110 command command register 0nnn0111 hoffset horizontal offset 0nnn1000 voffset vertical offset 0nnn1001 shrsrc shared buffer source channel (0, 2, 4, 6) for even channels, (1, 3, 5, 7) for odd channels 0nnn1010 shrbegh shared buffer beginning line high 0nnn1011 shrbegl shared buffer beginning line low 0nnn1100 shrendh shared buffer end line high 0nnn1101 shrendl shared buffer end line low 0nnn1110 reserved reserved 0nnn1111 reserved reserved table 2. channel-n block register map address channel 0000xxxx 0 0001xxxx 1 0010xxxx 2 0011xxxx 3 0100xxxx 4 0101xxxx 5 0110xxxx 6 0111xxxx 7 1000xxxx multichannel 1001xxxx to 1111xxxx reserved addresses table 3. channel block addressing note: nnn = 000 to 111 for channels 0 to 7, respectively.
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 13 command the channel command register allows writing and read- ing of quad pixel data into external sdram memory. the read and write operations are described below: writing 0000 0010 to the command register caus- es the pixel data in qph and qpl to be stored into external sdram memory. writing 0000 0001 to the command register copies from external sdram memory the quad pixels spec- ified by qphoriz/qpline into qph/qpl. writing 0000 0011 to command register causes a write followed by a readback to verify the data. address name description 10000000 qph quad pixel high data read/write for multiple write 10000001 qpl quad pixel low data read/write for multiple write 10000010 qphoriz quad pixel within h line address 10000011 qplineh quad pixel line address high 10000100 qplinel quad pixel line address low 10000101 losall loss-of-sync flags for channels 0 through 7 10000110 mwrite command register, triggers multiple write(s) 10000111 control control bits 10001000 to 10001111 reserved reserved registers table 4. multichannel block register map (common to all eight channels) qpline ntsc (voffset = 128) field, line pal (voffset = 133) field, line 0 0000 0000 0 0000 0001 field 1, line 21 field 2, line 21 field 1, line 26 field 2, line 26 0 0000 0010 0 0000 0011 field 1, line 22 field 2, line 22 field 1, line 27 field 2, line 27 0 1111 1110 0 1111 1111 field 1, line 148 field 2, line 148 field 1, line 153 field 2, line 153 1 1111 0010 field 2, line 263 1 1111 1111 field 2, line 276 table 5. qpline mapping the command register is described below: bit7 bit0 000000 write read hoffset the channel horizontal offset register defaults at power- up to 128. values less than 128 shift the osd image to the left (as viewed on the display), while values greater than 128 shift the osd image to the right. for example, changing hoffset from 128 to 110 shifts the image to the left by approximately 10% of the visible display. changing hoffset from 128 to 156 shifts the image to the right by approximately 10% of the visible display. the image portion shifted beyond the active video is automatically blanked on any edge. the units of hoff- set are in quad pixels. horizontal offset is used to allow flexibility in the video timing for various video sources. horizontal offset ensures that the first logical osd pixel is visible on the left-hand edge of the video monitor screen.
max4455 arbitrary graphics on-screen display video generator 14 ______________________________________________________________________________________ shrbegh, shrbegl share begin line hi, share begin line lo. this register pair contains a 9-bit address, which specifies the start- ing horizontal line to be used from the shared video frame buffer memory. shrbeg hi contains only 1 bit, which resides in the lsb position (bit 0) of the shrbeg hi register. the lower 8 bits of the 9-bit address are specified by shrbeg lo. valid shared line numbers range from 0 to 483 ntsc (511 pal). the async flag in the channel status register controls the time of actual update, either immediate (asynchronous) or video field synchronous. shrbegh contains the upper bits of the starting line address and shrbegl contains the lower bits of the line starting address. to allow the entire value to be changed at once, the internal value of shrbeg (which uses both shrbegh and shrbegl) is not updated until shrbegl is written. a write to shrbegh alone does not trigger an update of the internal shrbeg value. shrendh, shrendl this register pair, share end line hi, share end line lo, contains a 9-bit address, which specifies the ending horizontal line to be used from the shared video frame buffer memory. shrend hi contains only 1 bit, which resides in the lsb position (bit 0) of the shrend hi register. the lower 8 bits of the 9-bit address are speci- fied by shrend lo. valid shared line numbers range from 0 to 483 visible ntsc (511 pal). the async flag in the channel status register controls the time of actual update, either immediate (asynchronous) or video field synchronous. to allow the entire value to be changed at once, the internal value of shrend (which uses both shrendh and shrendl) is not updated until shrendl is written. a write to shrendh alone does not trigger an update of the internal shrend value. the shared memory source channel register is described below: bit7 bit0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 voffset the channel vertical offset register defaults at power-up to 128. values less than 128 shift the image up while values greater than 128 shift the osd image down. for example, changing voffset from 128 to 80 shifts the image up by approximately 10% of the visible display. changing voffset from 128 to 176 shifts the image down by approximately 10% of the visible display. this register controls the vertical offset of the osd graphics insertion video. the units of voffset are logical lines. vertical offset ensures that the first logical osd graph- ics line is visible on the video monitor screen. updates to voffset can take up to two full frame periods to take effect. shrsrc shared memory source channel. a nonzero value in shrsrc replaces a horizontal band of display with data from another channel. when an shrsrc channel is selected (nonzero value in the shrsrc register), the channel s graphics video is generated from the chan- nel s memory, except for the horizontal video lines between (and including) shrbegh/l and shrendh/l, which instead comes from the memory channel speci- fied by the shrsrc register (see applications information for more details on how video memory shar- ing works). time of actual update, either immediate (asynchronous) or field synchronous, is controlled by the async flag in the channel command register. even channels can only be shared with even channels. odd channels can only be shared with odd channels. note: if multiple even or odd channels are set to 1, data is taken from the lowest even channel and shared with the higher even channels. this is also true for the odd channels.
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 15 losall this register is common to all eight channels and reflects the status of sync presence on each of the eight vidin_ inputs. if valid composite sync is present at each of the eight vidin_ inputs, this register contains all zeros. if any channel loses sync for more than one horizontal line period, a flag is set for that respective channel indicating sync loss. normally, the host processor polls this register periodically and checks for nonzero flag bits, indicating loss of video on any or all channels. this feature detects vandalism, security threats, or simple camera/link failure. the loss of sync register is described below: mwrite multiple write command register. trigger multiple write operations to osd frame buffer memory by writing to mwrite, specifying which channels should receive data. this is useful in updating graphics common to multiple channels (i.e., time of day, etc.). writing a 1 triggers writes to the desired channel as defined below. this register autoclears itself after a multiple write cycle completes. the multiple write register is described below: control control bits for the multichannel block register. vinc, when set to 1, enables autoincrement of qplineh/l in the multichannel block after each host multichannel write to osd memory. hinc, when set to 1, enables autoincrement of qphoriz in the multichannel block after each host multichannel write operation to osd buffer memory. the control register is described below: bit7 bit0 0 0 0 vinc hinc 0 0 0 bit7 bit0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 bit7 bit0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 detailed description of the multichannel block registers qph, qpl pixel data is read/written 16 bits at a time to the quad pixel registers due to the sdram memory organization. the most significant 4 bits (nybble) of qph represents the leftmost pixel and the least significant 4 bits of qpl represents the rightmost pixel (4 bits per pixel). table 1 shows pixel data mapping. qph and qpl for the multi- channel block is read/written the same as the individual channel-n register function, except multichannel pixel data is used for multiple write operations to selected channels. qphoriz this 8-bit value is the address of the quad pixel within the line specified by qpline hi and qpline lo. a zero value in qphoriz addresses the leftmost dis- played quad pixel in the specified line and increasing qphoriz addresses indexes towards the right-hand side of the video screen. this register addresses multi- channel write operations. valid values range from zero to 177. write a 1 in the hinc bit of the multichannel control register to enable autoincrement of qphoriz. qphoriz autoincrement saturates at 177. qplineh, qplinel this 9-bit address specifies the horizontal line of the quad pixel to be accessed (host read or write). qpline hi is only 1 bit that resides in the lsb (bit 0) of the qpline hi register. the lower 8 bits of the 9-bit address are specified by qpline lo. valid displayed line numbers range from 0 to 483 ntsc (511 pal). this register is used for addressing for multichannel write operations. write a 1 in the vinc bit of the channel control register to enable autoincrement of qpline_. qpline_ autoincrement saturates at 511.
max4455 arbitrary graphics on-screen display video generator 16 ______________________________________________________________________________________ applications information interfacing to maxim video crosspoint switches the max4455 interfaces directly to max4356/max4358 video crosspoint switches with osd insertion function (figure 7). the max4455 osdkey_ and osdfill_ out- puts connect directly to the osdkey_ and osdfill_ inputs on the max4356/max4358 and utilize the inter- nal fast mux in the max4356/max4358 to implement the osd insertion. to ensure correct video timing, the max4455 vidin_ input senses and extracts the video timing directly from the crosspoint switch output. interfacing the max4455 with a fast mux switch the max4455 interfaces directly to a fast mux switch, as shown in figure 8. choose a device with a switch time of less than 30ns, such as the max4258, for accurate osd insertion. the max4258 is a single-channel wideband video amplifier with input multiplexing and a channel-to- channel switching time of 20ns. configure the amplifier using external resistors for a 6db gain to drive a 75 ? back-terminated video line. connect the osdfill_ output of the max4455 to in0 of the max4258 and conn ect the video source (camera output) to in1. connect the osdkey_ output of the max4455 to a0, the channel select input of the max4258. when the osdkey_ signal is low, the osdfill_ analog signal on channel in0 pass- es through the mux and the osd information is inserted into the video image. when the osdkey_ signal is high, the camera video output passes through the mux and is displayed on the monitor. channel blanking during video input source switching before switching input video sources on a channel with active osd, set the blank bit to 1 in the channel sta- tus register to prevent osdkey assertion during the video blanking interval. failure to blank the osd prior to switching input video sources can cause osd infor- mation to be inserted over the new video input s vertical blanking interval, resulting in a loss of sync on that channel. the max4455 timing synchronizes to the video output of the channel, such that switching anoth- er asynchronous input video source can cause writing of osd information over the new video source with unpredictable results (i.e., osd insertion over the verti- cal blanking interval). the channel blanking procedure follows: 1) set blank = 1. 2) switch camera/video source input. 3) set blank = 0. portion of memory allocated to channel micro- controller memory interface video timing extraction and control digital line buffers 4-bit d/a max4455 osd channel-n *optional components. used to attenuate the color burst signal of color cameras to avoid false triggering of the sync detector in the max4455. max4358 video crosspoint switch camera osdfill_ (fast mux) osdkey_ 0.1 f 470pf* camera +osd cpu interface vidin_ v k1 v dd v dd switch matrix 75 ? 430 ? * figure 7. interfacing max4455 with max4358 video crosspoint switch
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 17 the result of writing osd over the vertical blanking interval is a rolling picture that the display monitor can- not sync to, and the max4455 loss-of-sync flag is set for that channel. reestablish sync by blanking the channel s osd for at least one full video frame period, allowing the max4455 s sync timing circuitry to correct- ly sense the new video source s timing, and reset the los flag. optimizing osdfill load termination and r rset the max4455 provides standard 100 ire (0.714v) full- scale osdfill_ output levels with r rset = 11.75k ? and osdfill_ terminated with r osdfill_ = 75 ? to agnd. the max4455 osdfill_ outputs can drive as high as 1.5v by selecting a lower r rset value, or increasing the value of r osdfill , or a combination of both. osdfill output levels higher than 0.714v can have increased dis- tortion and degraded linearity (see the osdfill_ reference voltage (rset) section). sdram memory selection the max4455 ev kit uses the micron mt48lc1m16tg- 7s sdram. the max4455 has not been tested with, but is designed to operate with the following sdrams: micron mt48lc1m16a1-8 or faster, vis vg3617161dt-8 or faster, hyundai hy57v161610d or hy57v161610c, mitsubishi m2v64s40dtp, micron mt48lc4m16a2, and hitachi hm5264165f. anti-aliasing and flicker the max4455 is a high-resolution graphics system capable of accurately displaying a single pixel line. a line with the height of one pixel, by definition, occurs only on one of the two interlaced fields that make up the standard interlaced video signal. since the interlaced system has a frame rate of about 60hz, the field rate is half of this (30hz). any object occurring only on one field is displayed at a 30hz rate, resulting in a flickering image. any signal displayed at less than a 50hz rate is perceived to visibly flicker. the slower the display rate is, the higher the perceived flicker. the amount of flicker in a one-pixel-high horizontal line is dependent on the length of the line. the flicker asso- ciated with very short lines that are part of another shape are typically very minimal. for example, the flick- er of the legs of the letter f is almost imperceptible. at the other extreme, a one-pixel horizontal line that spans the width of a display exhibits flicker that can be very noticeable. the perceived flicker due to thin horizontal lines can be minimized by making the line thicker or by using anti- aliasing techniques. for the best results, these two max4258 fb to max4455 vidin_ input osdfill_ (from max4455) switch matrix +1 in0 out1 in1 +1 +5v 510 ? 510 ? 75 ? -5v ao osdkey_ (from max4455) camera figure 8. interfacing max4455 with a fast mux switch
max4455 arbitrary graphics on-screen display video generator 18 ______________________________________________________________________________________ techniques can be used in conjunction. a thicker line exhibits much less of the flicker effect. once the line is from five to six lines thick, the additional improvement from thicker lines is negligible. anti-aliasing is a fairly well-known technique that involves decreasing the severity of the transition of the graphic or font structure. here, it involves bracketing a horizontal line with two or more other lines that have a relative bright- ness that is between the brightness level of the line and the background. this is illustrated in figure 9. the proper application of this technique softens the look of the line, which can be undesirable in some cases. in general, it makes the display easier to read. finite switch time effects the max4455 generates the osdfill_ and osdkey_ signals time coincident with each other within a few nanoseconds. since the osdkey_ signal controls when the external fast mux switch switches from normal camera video to the osdfill signal, any finite delay in the response time of this fast mux switch has an effect on the resulting osd insertion (figure 10). due to the finite switching time of the fast mux switch, both the leading and trailing portions of the osdfill_ are inserted slightly later in time. the leading edge does not create a visible artifact on the screen since it only shifts the image to the right an amount equal to the switch delay. the trailing edge of the osdfill_ can result in a visible artifact because the osdfill_ signal has already returned to 0 ire before the fast mux switch can transition back to the camera video signal. this effect is shown in figure 11. in a typical ntsc system with a bandwidth of 4.2mhz, the narrowest resolved image is about 120ns wide. if the delay of the fast mux switch is less than half of this, 60ns or less, no visible artifact should be seen on the display. the displayed information can be designed to dramati- cally minimize the adverse effect of the finite switch time, if desired. for example, virtually all fonts and graphics that are overlayed on normal video need to be outlined for good readability. a very common technique is to use white structures with a black outline border. to compen- sate for the above finite switch time effect, construct the graphic or font with a thinner trailing edge. when dis- played, it looks symmetrical with the trailing edge appear- ing normal. figure 12 illustrates this technique. memory sharing memory sharing is a feature that reduces the host processor burden for tasks such as time-stamp update. the max4455 supports user-specified starting and ending lines to be shared by any number of channels. in figure 13, the time stamp is written only to channel 0 on line start through line end. graphics data stored in lines outside of start and end remain unique for each of the eight video channels (figure 13). in figure 13, channel 0 s start line number through end line number are duplicated onto channel 2 and channel 4 s display. the source of shared data is defined in the shrshc register (see the max4455 registed descrip- tion section). for example, channel 15 can be pro- grammed to display channel 7 s graphics beginning at channel 7 start line #n through end line #m, etc. sharing is restricted to even channels with even chan- nels and odd channels with odd channels. for exam- ple, channels 1, 3, 5, 7 can share lines and channels 0, 2, 4, 6 can share lines in any combination. power supplies and bypassing the max4455 operates from a single 2.7v to 5.5v analog supply and a 3v to 3.6v digital supply. additional logic supplies for host p interface (v h1 ) and the osdkey_ interface (v k1 ) allow the max4455 to interface with other logic supplies from 2.7v to 5.5v. bypass each supply pin with a 0.1f capacitor to ground. layout concerns for best performance, make the osdfill_ and osd- key_ output traces as short as possible, and place the 75 ? termination resistor close to the crosspoint switch osdfill_ input with the resistor terminated to the solid analog ground plane. the sdram interface is the high- est speed connection and therefore requires careful layout. place the sdram close to the max4455 to mini- mize trace lengths. the max4455 pinout is optimized for memory bus trace routing to the sdram without crossing traces. refer to the max4455 ev kit for a proven pc board layout.
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 19 regular line anti-aliased line figure 9. anti-aliased line drawing figure 10. finite switch time effects camera video osd fill osd key camera + osd fill 0 ire 70 ire 0 ire 70 ire fast mux switch 0 ire 100 ire 100 ire camera osd fill t d t d t d = switch delay ideal effect of finite switch delay figure 11. finite switch delay visual effect osd result compensated memory data figure 12. compensated graphics example
max4455 arbitrary graphics on-screen display video generator 20 ______________________________________________________________________________________ programming examples the max4455 ev kit provides a high-level user inter- face with free-hand drawing, bit-mapped graphics, and text-insertion tools. listings 1 through 5 show some pseudocode examples based on the max4455 ev kit source code for low-level register access, line drawing, rgb-to-gray-scale conversion, and block memory transfer to the osd. //--------------------------------------------------------------------------- // max4455 per-channel registers const unsigned __int8 ch_qph = 0x00 ; // quad pixel high (msb = left pixel) const unsigned __int8 ch_qpl = 0x01 ; // quad pixel low (lsb = right pixel) const unsigned __int8 ch_qphoriz = 0x02 ; // quad pixel horizontal address 0..177 const unsigned __int8 ch_qplineh = 0x03 ; // quad pixel line address 0..483 (511 pal) const unsigned __int8 ch_qplinel = 0x04 ; // low byte of qpline const unsigned __int8 ch_status = 0x05 ; // status { 0 0 0 vinc hinc async blank los } const unsigned __int8 ch_status_vinc = 0x10 ; // auto-increment vertical const unsigned __int8 ch_status_hinc = 0x08 ; // auto-increment horizontal const unsigned __int8 ch_status_async = 0x04 ; // asynchronous write const unsigned __int8 ch_status_blank = 0x02 ; // supress on-screen display const unsigned __int8 ch_status_los = 0x01 ; // (read-only) loss of sync const unsigned __int8 ch_command = 0x06 ; // command { 0 0 0 0 0 0 write read } const unsigned __int8 ch_command_write = 0x02 ; const unsigned __int8 ch_command_read = 0x01 ; const unsigned __int8 ch_hoffset = 0x07 ; // horizontal offset (128u = zero offset) const unsigned __int8 ch_voffset = 0x08 ; // vertical offset (128u = zero offset) const unsigned __int8 ch_shrsrc = 0x09 ; // shared buffer source const unsigned __int8 ch_shrbegh = 0x0a ; // shared buffer beginning line const unsigned __int8 ch_shrbegl = 0x0b ; // const unsigned __int8 ch_shrendh = 0x0c ; // shared buffer end line const unsigned __int8 ch_shrendl = 0x0d ; // // max4455 channel register banks const unsigned __int8 ch0_regs = 0x00 ; // register base for channel 0 registers const unsigned __int8 ch1_regs = 0x10 ; // register base for channel 1 registers const unsigned __int8 ch2_regs = 0x20 ; // register base for channel 2 registers const unsigned __int8 ch3_regs = 0x30 ; // register base for channel 3 registers const unsigned __int8 ch4_regs = 0x40 ; // register base for channel 4 registers const unsigned __int8 ch5_regs = 0x50 ; // register base for channel 5 registers const unsigned __int8 ch6_regs = 0x60 ; // register base for channel 6 registers const unsigned __int8 ch7_regs = 0x70 ; // register base for channel 7 registers const unsigned __int8 mwrite_regs = 0x80 ; // register base for multi-channel write listing 1. constant definitions
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 21 // max4455 all-channel registers const unsigned __int8 losall = 0x85 ; // loss of sync { ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 } const unsigned __int8 losall_ch7 = 0x80 ; const unsigned __int8 losall_ch6 = 0x40 ; const unsigned __int8 losall_ch5 = 0x20 ; const unsigned __int8 losall_ch4 = 0x10 ; const unsigned __int8 losall_ch3 = 0x08 ; const unsigned __int8 losall_ch2 = 0x04 ; const unsigned __int8 losall_ch1 = 0x02 ; const unsigned __int8 losall_ch0 = 0x01 ; const unsigned __int8 mwrite = 0x86 ; // multiple write { ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 } const unsigned __int8 mwrite_ch7 = 0x80 ; const unsigned __int8 mwrite_ch6 = 0x40 ; const unsigned __int8 mwrite_ch5 = 0x20 ; const unsigned __int8 mwrite_ch4 = 0x10 ; const unsigned __int8 mwrite_ch3 = 0x08 ; const unsigned __int8 mwrite_ch2 = 0x04 ; const unsigned __int8 mwrite_ch1 = 0x02 ; const unsigned __int8 mwrite_ch0 = 0x01 ; const unsigned __int8 control = 0x87 ; // auto-increment for mwrite { 0 0 0 vinc hinc 0 0 0 } const unsigned __int8 control_vinc = 0x10 ; const unsigned __int8 control_hinc = 0x08 ; listing 1. constant definitions (continued)
max4455 arbitrary graphics on-screen display video generator 22 ______________________________________________________________________________________ //--------------------------------------------------------------------------- // example code: low-level register access. // the max4455 evaluation software uses a bidirectional parallel port under windows. // practical applications should use a microprocessor memory or i/o bus. // user-defined subroutine to wait until ready/busy signal is ready. // return false if the busy signal seems to be stuck low. extern bool wait_until_ready (void); // user-defined subroutines to read and write the host data bus extern void set_data (int value ); extern int get_data (void); // user-defined subroutine to write the host control lines extern void set_control (int value ); // example control bus state values. #define addr 0x80 #define data 0x00 #define wr_low 0x00 #define wr_high 0x40 #define rd_low 0x00 #define rd_high 0x20 #define cs 0x01 // control bus state when writing a max4455 register address unsigned char ucctrl8_addr_wr = addr | wr_low | rd_high | cs ; // control bus state when idle after writing address unsigned char ucctrl8_addr_idle = addr | wr_high | rd_high | cs ; // control bus state when writing max4455 register data unsigned char ucctrl8_data_wr = data | wr_low | rd_high | cs ; // control bus state when reading max4455 register data unsigned char ucctrl8_data_rd = addr | wr_high | rd_low | cs ; // control bus state when idle after reading or writing data unsigned char ucctrl8_data_idle = addr | wr_high | rd_high | cs ; listing 2. low-level register access
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 23 bool try_dut_register_write (const int addr8 , const int data8 ) { if ( wait_until_ready () == false) return false; set_control ( ucctrl8_addr_wr ); set_data ( addr8 ); set_control ( ucctrl8_addr_idle ); if ( wait_until_ready () == false) return false; set_control ( ucctrl8_data_wr ); set_data ( data8 ); set_control ( ucctrl8_data_idle ); return true; } bool try_dut_register_read (const int addr8 , int* ptrdata ) { int ucdata8 ; if ( wait_until_ready () == false) return false; set_control ( ucctrl8_addr_wr ); set_data ( addr8 ); set_control ( ucctrl8_addr_idle ); if ( wait_until_ready () == false) return false; set_control ( ucctrl8_data_rd ); ucdata8 = get_data (); set_control ( ucctrl8_data_idle ); (* ptrdata ) = ucdata8 ; return true; } listing 2. low-level register access (continued)
max4455 arbitrary graphics on-screen display video generator 24 ______________________________________________________________________________________ //--------------------------------------------------------------------------- //--------------------------------------------------------------------------- // example code: drawing a horizontal line. // external definitions required for: // read_register // write_register //--------------------------------------------------------------------------- // drawing primitives for on-screen display memory // draw a line in the osdevkit's display memory. void osd_hline (int ch_base , int xleft , int xright , int y ) { // in the status register, set hinc=1 and clear vinc=0 unsigned __int8 status = read_register ( ch_base | ch_status ); status &=~ ch_status_vinc ; status |= ch_status_hinc ; write_register ( ch_base | ch_status , status ); unsigned char linel = y & 0xff ; unsigned char lineh = ( y & 0x100 ) >> 8 ; write_register ( ch_base | ch_qplineh , lineh ); write_register ( ch_base | ch_qplinel , linel ); unsigned char horiz = (int) ( floor ( xleft / 4.0 + 0.5 )) & 0xff ; write_register ( ch_base | ch_qphoriz , horiz ); int width = xright - xleft ; width = (int) ( floor ( width / 4.0 + 0.5 )); while( width -- > 0 ) { // under windows, be a good citizen and service the message quque. application -> processmessages (); if ( application -> terminated ) break; write_register ( ch_base | ch_command , ch_command_write ); } } listing 3. horizontal line draw
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 25 //--------------------------------------------------------------------------- //--------------------------------------------------------------------------- // example code: copying a block from host memory to the on-screen display. // external definitions required for: // read_register // write_register // get_quadpixels (x, y, nybble_3, nybble_2, nybble_1, nybble_0); //--------------------------------------------------------------------------- // copy a rectangular area from pc memory to the on screen display memory // registers affected: ch_status, ch_qph, ch_qpl, ch_qplineh, ch_qplinel, ch_qphoriz void osd_from_win (int ch_base , tcanvas * canvas , int xleft , int ytop , int xright , int ybottom ) { // in the status register, set hinc=1 and clear vinc=0 unsigned __int8 status = read_register ( ch_base | ch_status ); status &=~ ch_status_vinc ; status |= ch_status_hinc ; write_register ( ch_base | ch_status , status ); // make sure that xleft and xright are on quad pixel boundaries xleft = (int) ( floor ( xleft / 4.0 + 0.5 )) * 4 ; xright = (int) ( floor ( xright / 4.0 + 0.5 ) + 1 ) * 4 ; for (int y = ytop ; y <= ybottom ; y ++) { // under windows, be a good citizen and service the message quque. application -> processmessages (); if ( application -> terminated ) return; unsigned char linel = y & 0xff ; unsigned char lineh = ( y & 0x100 ) >> 8 ; write_register ( ch_base | ch_qplineh , lineh ); write_register ( ch_base | ch_qplinel , linel ); unsigned char horiz = (int) ( floor ( xleft / 4.0 + 0.5 )) & 0xff ; write_register ( ch_base | ch_qphoriz , horiz ); for (int x = xleft ; x <= xright ; x += 4 ) { // in the max4455 evaluation software, // the picture is copied from the host's screen. // a real application would replace win_get_quadpixels with // an application-specific data generating routine. int nybble_3 , nybble_2 , nybble_1 , nybble_0 ; get_quadpixels ( x , y , nybble_3 , nybble_2 , nybble_1 , nybble_0 ); unsigned __int8 qph = nybble_3 * 0x10 + nybble_2 ; unsigned __int8 qpl = nybble_1 * 0x10 + nybble_0 ; write_register ( ch_base | ch_qph , qph ); write_register ( ch_base | ch_qpl , qpl ); write_register ( ch_base | ch_command , ch_command_write ); } } } listing 4. rectangle block copy
max4455 arbitrary graphics on-screen display video generator 26 ______________________________________________________________________________________ //--------------------------------------------------------------------------- //--------------------------------------------------------------------------- // example code: converting rgb values to 4-bit key+luma control value. //--------------------------------------------------------------------------- // convert tcolor (rgb) to a 4-bit color value for the max4455 // // this 4-bit value controls osdfill and osdkey as follows: // // 0000 transparent // 0001 black // 0010 lighter black // 0111 medium gray // 1110 lightest gray // 1111 white // // the rgb equations are based on keith jack's book, // video demystified, chapter 3, "color spaces", // which is copyright 2001 llh technology publishing. // isbn: 1-878707-56-6 // url: http://www.video-demystified.com/ // unsigned __int8 rgb_to_osdfill ( tcolor color ) { unsigned __int8 osd_control_value ; if ( color == cltransparent ) { osd_control_value = 0 ; // transparent } else { // convert tcolor into red, green, blue values in the range 0..255 unsigned __int8 red = ( color >> 0 ) & 0xff ; unsigned __int8 green = ( color >> 8u ) & 0xffu ; unsigned __int8 blue = ( color >> 16u ) & 0xffu ; const double ar = 0.299 , ag = 0.587 , ab = 0.114 , offset = 0 ; double luma = ar * red + ag * green + ab * blue + offset ; // maximum luma value is 255 unsigned __int8 greyscale_nybble = (( luma * 16.0 ) / 256 ) + 0.5 ; if ( greyscale_nybble > 15 + 1 ) { greyscale_nybble = 15 + 1 ; // white limit } if ( greyscale_nybble < 1 + 1 ) { greyscale_nybble = 1 + 1 ; // black limit } osd_control_value = greyscale_nybble - 1 ; } return osd_control_value ; } listing 5. converting rgb to 4-bit gray scale
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 27 12:30:59 pm channel 0 memory buffer channel 2 memory buffer channel 4 memory buffer 12:30:59 pm start line no. end line no. 12:30:59 pm start line no. end line no. chip information transistor count: 197,669 process: cmos figure 13. example of osd memory sharing
max4455 arbitrary graphics on-screen display video generator 28 ______________________________________________________________________________________ pin configuration av dd osdfill7 osdfill6 osdfill5 osdfill4 osdfill3 osdfill2 osdfill1 osdfill0 av dd rset agnd vidin7 vidin6 vidin5 vidin4 vidin3 vidin2 vidin0 vidin1 v h1 cs wr rd ad7 ad6 ad5 rdy/bsy d2 d3 d1 d4 d5 d6 ad4 ad3 ad2 ad1 ad0 addr/data dgnd dv dd d14 d13 d12 d11 d10 d9 d8 dqm d7 d15 clk a9 a8 a7 a6 a5 a4 we a2 a1 a0 a10 ba cas ras a3 dv dd dgnd osdkey7 osdkey6 osdkey5 osdkey4 osdkey3 osdkey2 osdkey1 osdkey0 xtal2 xtal1/sync av dd av dd av dd av dd av dd av dd av dd d0 dgnd dv dd dgnd dgnd dv dd dgnd dv dd dgnd v k1 dgnd dv dd dgnd top view tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 max4455
max4455 arbitrary graphics on-screen display video generator ______________________________________________________________________________________ 29 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 14x14x1.00l tqpf, exp. pad.eps
max4455 arbitrary graphics on-screen display video generator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 30 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max4455 part number table notes: see the max4455 quickview data sheet for further information on this product family or download the max4455 full data sheet (pdf, 672kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max4455ec q+td -40c to +85c rohs/lead-free: yes max4455ec q-t -40c to +85c rohs/lead-free: no max4455ec q+d tqfp;100 pin;14x14x1.0mm dwg: 21-0116d (pdf) use pkgcode/variation: c 100e+6 * -40c to +85c rohs/lead-free: yes materials analysis max4455ec q -40c to +85c rohs/lead-free: no didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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